This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-348932, filed Nov. 29, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device, and in particular, to a NAND type EEPROM and its deletion verification method.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a NAND type EEPROM (Electrically Erasable and Programmable Read Only Memory) as an example of a conventional non-volatile semiconductor storage device.
In the NAND type EEPROM, a NAND column is composed of memory cell transistors M1, M2, . . . , M8 connected in series by connecting their sources and drains together. Word lines WL1, WL2, . . . , WL8 are connected to gates of the memory cell transistors M1 to M8, respectively.
Selection gate transistors ST1k and ST2k are connected to the opposite ends, respectively, of the NAND column. Selection gate lines SG1 and SG2 are connected to gates of the section gate transistors ST1k and ST2k, respectively. A bit line BLk is connected to the selection gate transistor ST1k. A common source line SL is connected to the selection gate transistor ST2k.
Further, a plurality of other NAND columns are arranged adjacent to the above NAND column. A selection gate transistor ST1kxe2x88x921 or ST1k+1 is connected to one end of each of the plurality of NAND columns. Bit lines BLkxe2x88x921 and BLk+1 are connected to the selection gate transistors ST1kxe2x88x921 and ST1k+1, respectively. Furthermore, a selection gate transistor ST2kxe2x88x921 or ST2k+1 is connected to the other end of each of the plurality of NAND columns. A common source line S1 is connected to the selection gate transistors ST2kxe2x88x921 and ST2k+1.
Furthermore, work lines WL1 to WL8, the selection gate lines SG1 and SG2, bit lines BLkxe2x88x921, BLk, and BLk+1, and the common source line SL are provided with drive circuits 101, 102, 103, and 104, respectively.
With this configuration, adjacent cell transistors can share their sources and drains. This reduces the area of the transistors required for wiring. Thus, the NAND type EEPROM is characterized by its structure suitable for increased density. Further, the gate potentials of a large number of cell transistors can be simultaneously driven via the word lines WL1, WL2, . . . , WL8. Accordingly, data can be written to a large number of cell transistors at high speed or can be deleted or read from them at high speed.
FIG. 2 is a time chart showing the case in which a read operation is performed in the NAND type EEPROM.
A NAND type EEPROM composed of the series-connected cell transistors M1, M2, . . . , M8 is characterized in that to read data from a selected cell transistor, non-selected cell transistors in the same NAND column must be turned on and have their data read. That is, the word lines WL to the non-selected cell transistors are provided with a sufficiently high potential as a read potential Vread. Only the word line WL to the selected transistor is provided with a determination potential VWLread used to determine whether the data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
At this time, if the provided read potential Vread is not sufficiently high, the non-selected cell transistors are turned off. Consequently, no cell currents flow regardless of the threshold voltage of the selected cell transistor. On the other hand, if the non-selected cell transistors are not sufficiently turned on, so that a read operation is performed while much channel resistance is remaining, then a cell current flows through the non-selected cell transistors to reduce their voltages. This increases the source potential of the selected cell transistor.
In such a case, a back bias effect or the effect of a decrease in the gate-source potential of the selected cell transistor inconveniently causes the threshold voltage of the selected cell transistor to be detected to have a value larger than its original one. Thus, with the NAND type EEPROM, the set value for the read potential Vread is a very important device specification.
Next, FIG. 3 is a time chart for deletion verification in the NAND type EEPROM.
The deletion verification is an operation of determining whether or not a deleting operation has been successfully performed on all cell transistors, i.e. whether or not all cell transistors have negative threshold voltages. No negative potentials required for this determination can be output to the word lines of the NAND type EEPROM. Thus, an approach different from the above read method is required in order to determine whether or not the cell transistors have negative threshold values. First, a high potential is provided to the common source line SL to set the bit lines BLk at a predetermined low potential. Subsequently, by setting the potentials at the word lines WL and selection gates SG1 and SG2 in a selected NAND column, to appropriate values, a cell current flows from the common source line SL to the bit line BLk to charge this line BLk. As a result, the potential across the bit line BLk increases from a small value to provide a back bias effect. This makes it possible to detect a threshold voltage lower than the set word line potential (see, for example, Jpn. Pat. Appln. KOKAI Publication Nos. 7-161852 and 11-250676).
For the NAND type EEPROM, a minimum deletion size called a xe2x80x9cblockxe2x80x9d is specified. Normally, a deleting operation is simultaneously performed on all cell transistors in the same NAND column. Subsequently, a read operation is performed by providing a sufficiently low determination potential VWLev to all word lines WL1 to WL8 in the NAND column. All cell transistors in the NAND column can have their threshold voltages determined at once by providing the same potential to all word lines. As a result, deletion verification can be carried out at high speed.
In the NAND type EEPROM, if a read operation is performed as described above, the effect of the previously described cell channel resistance is not negligible. In particular, if data is barely deleted from the cell transistors, the cell transistors have the maximum channel resistance. Accordingly, the back bias effect in the NAND column increases the threshold voltages to cause it to be determined that the deletion has not been completed yet. As a result, in a deletion verification operation, a deletion determination is made after the deletion has progressed sufficiently deeply (over-deletion).
Thus, it is still impossible to perfectly reliably determine the threshold voltages of cell transistors for which a deletion determination is to be made. However, this is a condition that makes the deletion determination stricter. In other words, it can be determined that the deletion is sufficient, on the basis of the results of the deletion verification.
However, as the structures of cell transistors become finer and finer, the over-deletion poses a critical problem because it may degrade cell reliability. Further, to suppress the degradation of a mis-write characteristic associated with the finer structures of cell transistors, local self boost (LSB) writes have been developed which utilize the cutoff characteristic of the cell transistors. Thus, it has been desirable to set a lower limit value for the threshold voltages of cell transistors after deletion.
Thus, two requirements have arisen for the threshold voltages of cell transistors after deletion. That is, the threshold voltages must be deep enough to avoid a non-deletion state even with a change in surrounding environments and must also be shallow enough to obtain a sufficient cutoff characteristic at a predetermined gate voltage. To meet these requirements, it is an important object to improve the accuracy with which the threshold voltages of cell transistors are determined after deletion.
According to an aspect of the present invention, there is provided a non-volatile semiconductor storage device comprising a NAND column having a plurality of memory cell transistors connected in series by a current passage; a plurality of word lines connected to gates of the plurality of memory cell transistors in the NAND column; word line drive circuits which drive the plurality of word lines; a bit line connected to one end of the NAND column via a selection gate transistor; a bit line drive circuit which drives the bit line; a source line connected to the other end of the NAND column via a selection gate transistor; a source line drive circuit which drives the source line; and a potential supply circuit which supplies a potential to a semiconductor region in the NAND column in which the plurality of memory cell transistors are formed; wherein the word line drive circuits supply a low voltage to the plurality of word lines, wherein the potential supply circuit supplies a high potential higher than the low potential, to the semiconductor region in which the plurality of memory cell transistors are formed, to delete contents stored in the plurality of memory cell transistors, and wherein in deletion verification which verifies that the contents stored in the plurality of memory cell transistors have been deleted, a read is executed on each of the plurality of word lines, and in the read, the word line drive circuit provides the selected one of the plurality of word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.
Further, according to an aspect of the present invention, there is provided a deletion verification method for a non-volatile semiconductor storage device having a NAND column having a plurality of series-connected memory cell transistors connected in series by a current passage and a plurality of word lines connected to gates of the plurality of memory cell transistors in the NAND column, comprising:
supplying a low potential to the plurality of word lines, while supplying a high potential higher than the low potential, to a semiconductor region in which the plurality of memory cell transistors are formed, to delete contents stored in the plurality of memory cell transistors; and
in deletion verification, executing a read on each of the plurality of word lines, and in the read, providing the selected one of the plurality of word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.